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| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-07-04 18:54:58 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-07-09 13:49:31 +0200 |
| commit | 7df533a7e3d2216e860ecf147ae8cee49bf133e9 (patch) | |
| tree | 6a95385f018bca6963984ef1252fc3edc7f32ade /drivers/clk/meson/axg.h | |
| parent | 80d396b5118f448cb2206a509aba6917691a835e (diff) | |
| download | linux-stable-7df533a7e3d2216e860ecf147ae8cee49bf133e9.tar.gz linux-stable-7df533a7e3d2216e860ecf147ae8cee49bf133e9.tar.bz2 linux-stable-7df533a7e3d2216e860ecf147ae8cee49bf133e9.zip | |
clk: meson: add gen_clk
GEN_CLK is able to route several internal clocks to one of the SoC
pads. In the future, even more clocks could be made accessible using
cts_msr_clk - the clock measure block.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.h')
| -rw-r--r-- | drivers/clk/meson/axg.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 6e55ebd6c77d..1d04144a1b2c 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -131,8 +131,10 @@ #define CLKID_PCIE_PLL 76 #define CLKID_PCIE_MUX 77 #define CLKID_PCIE_REF 78 +#define CLKID_GEN_CLK_SEL 82 +#define CLKID_GEN_CLK_DIV 83 -#define NR_CLKS 82 +#define NR_CLKS 85 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/axg-clkc.h> |