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authorStephen Boyd <sboyd@codeaurora.org>2016-08-15 15:47:15 -0700
committerStephen Boyd <sboyd@codeaurora.org>2016-08-15 15:47:15 -0700
commitddf7e5377bef301158aa45b4c4bbc209c29f2de9 (patch)
tree65d2c96d39cd1aff87ba488b8ed3461765b88e32 /drivers/clk/meson
parent5a227cd1ab3693d36ac7a6f1fc4e21a7129f62f0 (diff)
parent33608dcd01d0c0eb3f2442d88c8a97f1195bd2d5 (diff)
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Merge branch 'clk-meson-gxbb' into clk-next
* clk-meson-gxbb: clk: gxbb: add MMC gate clocks, and expose for DT
Diffstat (limited to 'drivers/clk/meson')
-rw-r--r--drivers/clk/meson/gxbb.c9
-rw-r--r--drivers/clk/meson/gxbb.h7
2 files changed, 14 insertions, 2 deletions
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index a6afc3ecc2b9..b736277f0cf6 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -583,6 +583,9 @@ static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);
static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);
static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
+static MESON_GATE(emmc_a, HHI_GCLK_MPEG0, 24);
+static MESON_GATE(emmc_b, HHI_GCLK_MPEG0, 25);
+static MESON_GATE(emmc_c, HHI_GCLK_MPEG0, 26);
static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);
static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
@@ -748,6 +751,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
[CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
[CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
+ [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
},
.num = NR_CLKS,
};
@@ -847,6 +853,9 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_ao_ahb_bus,
&gxbb_ao_iface,
&gxbb_ao_i2c,
+ &gxbb_emmc_a,
+ &gxbb_emmc_b,
+ &gxbb_emmc_c,
};
static int gxbb_clkc_probe(struct platform_device *pdev)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index a2adf3448b59..217df516de44 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -172,7 +172,7 @@
/* CLKID_CPUCLK */
#define CLKID_HDMI_PLL 2
#define CLKID_FIXED_PLL 3
-#define CLKID_FCLK_DIV2 4
+/* CLKID_FCLK_DIV2 */
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
#define CLKID_FCLK_DIV5 7
@@ -262,8 +262,11 @@
#define CLKID_AO_AHB_BUS 91
#define CLKID_AO_IFACE 92
#define CLKID_AO_I2C 93
+/* CLKID_SD_EMMC_A */
+/* CLKID_SD_EMMC_B */
+/* CLKID_SD_EMMC_C */
-#define NR_CLKS 94
+#define NR_CLKS 97
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>