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| author | Simon Horman <horms+renesas@verge.net.au> | 2019-03-25 17:35:52 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-04-02 09:50:48 +0200 |
| commit | e0836e36384321ab1b4af05ab441c0c59a972596 (patch) | |
| tree | 224967635fbe234364de113cead66b9ac2a6f4a2 /drivers/clk/renesas/r8a774a1-cpg-mssr.c | |
| parent | 10d9ea5100c89afd677a202036e0e34e129a6c52 (diff) | |
| download | linux-stable-e0836e36384321ab1b4af05ab441c0c59a972596.tar.gz linux-stable-e0836e36384321ab1b4af05ab441c0c59a972596.tar.bz2 linux-stable-e0836e36384321ab1b4af05ab441c0c59a972596.zip | |
clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have come to have precisely
the same meaning. Remove this redundancy by eliminating the latter.
This is not expected to have any run-time effect.
As suggested by Geert Uytterhoeven.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a774a1-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a774a1-cpg-mssr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 8e7bb43b6848..44161fd0a09c 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -72,7 +72,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), |