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author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2020-08-31 19:03:12 +0100 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-09-04 09:42:01 +0200 |
commit | e8d8e9a3d0b28c99a0f0f7fc168fd6eff345fcc3 (patch) | |
tree | 766eb46eea36ffb5b21e66dccc9b86f527b89998 /drivers/clk/renesas/r8a7792-cpg-mssr.c | |
parent | 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff) | |
download | linux-stable-e8d8e9a3d0b28c99a0f0f7fc168fd6eff345fcc3.tar.gz linux-stable-e8d8e9a3d0b28c99a0f0f7fc168fd6eff345fcc3.tar.bz2 linux-stable-e8d8e9a3d0b28c99a0f0f7fc168fd6eff345fcc3.zip |
clk: renesas: r8a7742: Add clk entry for VSPR
Add clock entry 130 for VSPR (VSP for Resizing) module, so that this module
can be used on R8A7742 (RZ/G1H) SoC.
Alongside rename clock entry "vsp1-sy" to "vsps" (VSP Standard), so that
VSP1 clock names are in sync.
Note: The entry for VSPR clock was accidentally dropped from RZ/G manual
when all the information related to RT were removed.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200831180312.7453-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a7792-cpg-mssr.c')
0 files changed, 0 insertions, 0 deletions