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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-09-09 11:25:15 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-09-18 14:43:51 +0200 |
| commit | e46a1a9943c0e84f439b971d6ce03f87e3d67441 (patch) | |
| tree | 928afa94409bd2c9c2bdc27e43e198df0367655f /drivers/clk/renesas/r8a779g0-cpg-mssr.c | |
| parent | 36ff366033f0dde1e70d5ab96397803eb0399ddf (diff) | |
| download | linux-stable-e46a1a9943c0e84f439b971d6ce03f87e3d67441.tar.gz linux-stable-e46a1a9943c0e84f439b971d6ce03f87e3d67441.tar.bz2 linux-stable-e46a1a9943c0e84f439b971d6ce03f87e3d67441.zip | |
clk: renesas: r8a779g0: Add EtherAVB clocks
Add the module clocks used by the Ethernet AVB (EtherAVB-IF) blocks on
the Renesas R-Car V4H (R8A779G0) SoC.
Based on a larger patch in the BSP by Kazuya Mizuguchi.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e9382b0d9acc84acc2357a6921a1459f3a32240e.1662714852.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas/r8a779g0-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a779g0-cpg-mssr.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index d40ad40e4b76..9641122133b5 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -150,6 +150,9 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { + DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC), + DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC), + DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC), DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER), DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER), DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER), |