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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-10-07 12:14:34 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-10-08 15:10:36 +0200 |
| commit | 373bd6f487562e8727bc842e9983b093d57968cc (patch) | |
| tree | ee3fae4574573a3b47c47aafd688ea8230c5d709 /drivers/clk/renesas/rzg2l-cpg.h | |
| parent | eaff33646f4cb6a541d01013b0a222f03f6dfac3 (diff) | |
| download | linux-stable-373bd6f487562e8727bc842e9983b093d57968cc.tar.gz linux-stable-373bd6f487562e8727bc842e9983b093d57968cc.tar.bz2 linux-stable-373bd6f487562e8727bc842e9983b093d57968cc.zip | |
clk: renesas: r9a07g044: Add SDHI clock and reset entries
Add SDHI{0,1} mux, clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211007111434.8665-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 952fca98ba71..7fb6b4030f72 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -11,6 +11,7 @@ #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) +#define CPG_PL2SDHI_DSEL (0x218) #define CPG_CLKSTATUS (0x280) #define CPG_PL3_SSEL (0x408) #define CPG_PL6_ETH_SSEL (0x418) @@ -39,6 +40,9 @@ #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) +#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) +#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) + /** * Definitions of CPG Core Clocks * |