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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-09-22 16:51:42 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-09-24 15:11:05 +0200 |
| commit | 7c5a2561737d88b55764034b27f897498e90a319 (patch) | |
| tree | 3056b55c303f06fdf79b68c80aebf899ceb33ce1 /drivers/clk/renesas/rzg2l-cpg.h | |
| parent | 3ae4087bf46a8772695a0441f1654eacddd3e2bb (diff) | |
| download | linux-stable-7c5a2561737d88b55764034b27f897498e90a319.tar.gz linux-stable-7c5a2561737d88b55764034b27f897498e90a319.tar.bz2 linux-stable-7c5a2561737d88b55764034b27f897498e90a319.zip | |
clk: renesas: rzg2l: Add support to handle MUX clocks
Add support to handle mux clocks in order to select a clock source
from multiple sources.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 63695280ce8b..f538ffa3371c 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -24,6 +24,9 @@ #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) +#define SEL_PLL_PACK(offset, bitpos, size) \ + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) + /** * Definitions of CPG Core Clocks * @@ -43,6 +46,7 @@ struct cpg_core_clk { const struct clk_div_table *dtable; const char * const *parent_names; int flag; + int mux_flags; int num_parents; }; @@ -54,6 +58,9 @@ enum clk_types { /* Clock with divider */ CLK_TYPE_DIV, + + /* Clock with clock source selector */ + CLK_TYPE_MUX, }; #define DEF_TYPE(_name, _id, _type...) \ @@ -69,6 +76,11 @@ enum clk_types { #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ .parent = _parent, .dtable = _dtable, .flag = _flag) +#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \ + _mux_flags) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ + .parent_names = _parent_names, .num_parents = _num_parents, \ + .flag = _flag, .mux_flags = _mux_flags) /** * struct rzg2l_mod_clk - Module Clocks definitions |