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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-12-03 11:51:50 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-12-08 10:05:56 +0100 |
| commit | 7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0 (patch) | |
| tree | a38469ad418a14f0f444d18abb418bf861767b1a /drivers/clk/renesas/rzg2l-cpg.h | |
| parent | 98ee8b2f66ebff2fafe85668b9d00c3433b76566 (diff) | |
| download | linux-stable-7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0.tar.gz linux-stable-7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0.tar.bz2 linux-stable-7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0.zip | |
clk: renesas: r9a07g044: Add mux and divider for G clock
G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.
This patch adds a mux and divider for getting different rates from
this clock sources.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index fce4a8f35410..5729d102034b 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -12,9 +12,11 @@ #define CPG_PL1_DDIV (0x200) #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) +#define CPG_PL6_DDIV (0x210) #define CPG_PL2SDHI_DSEL (0x218) #define CPG_CLKSTATUS (0x280) #define CPG_PL3_SSEL (0x408) +#define CPG_PL6_SSEL (0x414) #define CPG_PL6_ETH_SSEL (0x418) #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) @@ -35,12 +37,14 @@ #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) +#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) #define SEL_PLL_PACK(offset, bitpos, size) \ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) +#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) #define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) |