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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-02-05 08:40:06 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-02-10 14:34:58 +0100 |
| commit | a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd (patch) | |
| tree | a90d6bd381ba4a19c2e448c31010cc70b02b94d8 /drivers/clk/renesas/rzg2l-cpg.h | |
| parent | fbf4ae93c2bca96035b2c36f408b0616403ede10 (diff) | |
| download | linux-stable-a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd.tar.gz linux-stable-a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd.tar.bz2 linux-stable-a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd.zip | |
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers to
control clocks and resets for the DRP-AI block.
Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same
between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take
care of the DRP-AI clocks/resets.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 5729d102034b..ce657beaf160 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -203,5 +203,6 @@ struct rzg2l_cpg_info { }; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; +extern const struct rzg2l_cpg_info r9a07g054_cpg_info; #endif |