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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-09-28 14:01:32 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-10-08 15:08:35 +0200 |
| commit | f294a0ea9d12a658ff326bbe0d64137659bc2fc9 (patch) | |
| tree | 63692058ef702cbd0dd38676dc49a08f85afb9b5 /drivers/clk/renesas/rzg2l-cpg.h | |
| parent | cc3e8f97bbd370b51b3bb7fec391d65d461d7d02 (diff) | |
| download | linux-stable-f294a0ea9d12a658ff326bbe0d64137659bc2fc9.tar.gz linux-stable-f294a0ea9d12a658ff326bbe0d64137659bc2fc9.tar.bz2 linux-stable-f294a0ea9d12a658ff326bbe0d64137659bc2fc9.zip | |
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller
Add clock and reset entries for SPI Multi I/O Bus Controller.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210928130132.15022-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 191c403aa52f..dc5b65a4029e 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -11,6 +11,7 @@ #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) +#define CPG_PL3_SSEL (0x408) #define CPG_PL6_ETH_SSEL (0x418) /* n = 0/1/2 for PLL1/4/6 */ @@ -24,10 +25,12 @@ #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) +#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) #define SEL_PLL_PACK(offset, bitpos, size) \ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) +#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) /** |