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authorGeert Uytterhoeven <geert+renesas@glider.be>2018-11-21 10:44:32 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2018-12-04 10:29:48 +0100
commit396bc9d40d694befa1c2c88f9873afc62a189b5f (patch)
treeb9dbf5cdeed9df733b7e3a35b1b880794fe87bce /drivers/clk/renesas
parentf70f4be7339dfca0ef684046c1583cce61b039fc (diff)
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clk: renesas: r8a77970: Add CPEX clock
Implement support for the CPEX clock on R-Car V3M. This clock can be selected as a clock source for CMT1 (Compare Match Timer Type 1). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/renesas')
-rw-r--r--drivers/clk/renesas/r8a77970-cpg-mssr.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index 9d845ebd7355..cbed3769a100 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -96,6 +96,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),