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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-12 09:05:05 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-26 12:38:01 +0200 |
| commit | 4ee04993aa83e5b260705a544007f7f6cfff0472 (patch) | |
| tree | c7de8715e9f20af0ca0748381b4edc2919c2a68c /drivers/clk/renesas | |
| parent | 0a5a00f042c474f3b865615a0662fc11db84b15f (diff) | |
| download | linux-stable-4ee04993aa83e5b260705a544007f7f6cfff0472.tar.gz linux-stable-4ee04993aa83e5b260705a544007f7f6cfff0472.tar.bz2 linux-stable-4ee04993aa83e5b260705a544007f7f6cfff0472.zip | |
clk: renesas: r8a779g0: Add SDHI clocks
Add the SD0H core clock and the SDHI module clock, which are used by the
SD Card/MMC Interface on the Renesas R-Car V4H (R8A779G0) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/e9b05d102160cc3f7395ac53a533e81c07307d5e.1665558175.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a779g0-cpg-mssr.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 5cc5ee1295d9..390162a07595 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -144,7 +144,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), - DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, CLK_SDSRC, 0x870), + DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870), + DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870), DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), @@ -180,6 +181,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("scif1", 703, R8A779G0_CLK_SASYNCPERD4), DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4), DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4), + DEF_MOD("sdhi", 706, R8A779G0_CLK_SD0), DEF_MOD("sydm0", 709, R8A779G0_CLK_S0D6_PER), DEF_MOD("sydm1", 710, R8A779G0_CLK_S0D6_PER), DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4), |