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| author | Phil Edworthy <phil.edworthy@renesas.com> | 2022-05-03 12:55:53 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:12:33 +0200 |
| commit | 63804400f2a5ababe596b4ec908321d6b54f45aa (patch) | |
| tree | 32cb17c6f483ef041f27e3df15f652b0f692c13e /drivers/clk/renesas | |
| parent | 75b0ad42ccd9a87873e91598116471d9991b09ea (diff) | |
| download | linux-stable-63804400f2a5ababe596b4ec908321d6b54f45aa.tar.gz linux-stable-63804400f2a5ababe596b4ec908321d6b54f45aa.tar.bz2 linux-stable-63804400f2a5ababe596b4ec908321d6b54f45aa.zip | |
clk: renesas: rzg2l: Make use of CLK_MON registers optional
The RZ/V2M SoC doesn't use CLK_MON registers, so make them optional.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-9-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r9a07g043-cpg.c | 2 | ||||
| -rw-r--r-- | drivers/clk/renesas/r9a07g044-cpg.c | 4 | ||||
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 8 | ||||
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.h | 3 |
4 files changed, 16 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 53a58034bef4..33c2bd8df2e5 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -315,4 +315,6 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = { /* Resets */ .resets = r9a07g043_resets, .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs = true, }; diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 8255b39dc147..b288897852c7 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -418,6 +418,8 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { /* Resets */ .resets = r9a07g044_resets, .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs = true, }; #ifdef CONFIG_CLK_R9A07G054 @@ -440,5 +442,7 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = { /* Resets */ .resets = r9a07g044_resets, .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs = true, }; #endif diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index a1e1fee9f483..48265276d169 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -926,6 +926,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) if (!enable) return 0; + if (!priv->info->has_clk_mon_regs) + return 0; + for (i = 1000; i > 0; --i) { if (((readl(priv->base + CLK_MON_R(reg))) & bitmask)) break; @@ -996,7 +999,10 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) if (clock->sibling) return clock->enabled; - value = readl(priv->base + CLK_MON_R(clock->off)); + if (priv->info->has_clk_mon_regs) + value = readl(priv->base + CLK_MON_R(clock->off)); + else + value = readl(priv->base + clock->off); return value & bitmask; } diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 59bbc8942e1d..43ce319a477f 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -236,6 +236,7 @@ struct rzg2l_reset { * @crit_mod_clks: Array with Module Clock IDs of critical clocks that * should not be disabled without a knowledgeable driver * @num_crit_mod_clks: Number of entries in crit_mod_clks[] + * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers */ struct rzg2l_cpg_info { /* Core Clocks */ @@ -256,6 +257,8 @@ struct rzg2l_cpg_info { /* Critical Module Clocks that should not be disabled */ const unsigned int *crit_mod_clks; unsigned int num_crit_mod_clks; + + bool has_clk_mon_regs; }; extern const struct rzg2l_cpg_info r9a07g043_cpg_info; |