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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2022-04-27 11:56:48 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2022-05-19 22:34:51 +0530 |
| commit | 885525c1e7e27ea6207d648a8db20dfbbd9e4238 (patch) | |
| tree | 9f2a34e759bde582f0a236a545074f2c4bbe18ca /drivers/clk/renesas | |
| parent | 7ac92262e1fb574ee4da2944b83e412aa0ae2ab4 (diff) | |
| download | linux-stable-885525c1e7e27ea6207d648a8db20dfbbd9e4238.tar.gz linux-stable-885525c1e7e27ea6207d648a8db20dfbbd9e4238.tar.bz2 linux-stable-885525c1e7e27ea6207d648a8db20dfbbd9e4238.zip | |
clk: renesas: r9a06g032: Export function to set dmamux
The dmamux register is located within the system controller.
Without syscon, we need an extra helper in order to give write access to
this register to a dmamux driver.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220427095653.91804-5-miquel.raynal@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r9a06g032-clocks.c | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index c99942f0e4d4..052d99059981 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -20,9 +20,12 @@ #include <linux/pm_clock.h> #include <linux/pm_domain.h> #include <linux/slab.h> +#include <linux/soc/renesas/r9a06g032-sysctrl.h> #include <linux/spinlock.h> #include <dt-bindings/clock/r9a06g032-sysctrl.h> +#define R9A06G032_SYSCTRL_DMAMUX 0xA0 + struct r9a06g032_gate { u16 gate, reset, ready, midle, scon, mirack, mistat; @@ -315,6 +318,30 @@ struct r9a06g032_priv { void __iomem *reg; }; +static struct r9a06g032_priv *sysctrl_priv; + +/* Exported helper to access the DMAMUX register */ +int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) +{ + unsigned long flags; + u32 dmamux; + + if (!sysctrl_priv) + return -EPROBE_DEFER; + + spin_lock_irqsave(&sysctrl_priv->lock, flags); + + dmamux = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); + dmamux &= ~mask; + dmamux |= val & mask; + writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); + + spin_unlock_irqrestore(&sysctrl_priv->lock, flags); + + return 0; +} +EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux); + /* register/bit pairs are encoded as an uint16_t */ static void clk_rdesc_set(struct r9a06g032_priv *clocks, @@ -963,7 +990,13 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) if (error) return error; - return r9a06g032_add_clk_domain(dev); + error = r9a06g032_add_clk_domain(dev); + if (error) + return error; + + sysctrl_priv = clocks; + + return 0; } static const struct of_device_id r9a06g032_match[] = { |