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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-02-16 16:20:18 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-10 17:07:07 +0100 |
| commit | 88ddf98aa511a5e0c2c76e5dfcf3c6b2581d0e85 (patch) | |
| tree | 552b812be03a9b1c11216bdeeb390ff0255177fe /drivers/clk/renesas | |
| parent | 1f04b7939704fce82d2bb5ef5561e2499a91170a (diff) | |
| download | linux-stable-88ddf98aa511a5e0c2c76e5dfcf3c6b2581d0e85.tar.gz linux-stable-88ddf98aa511a5e0c2c76e5dfcf3c6b2581d0e85.tar.bz2 linux-stable-88ddf98aa511a5e0c2c76e5dfcf3c6b2581d0e85.zip | |
clk: renesas: r8a77970: Add Z2 clock
Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3M, which
uses a fixed SYS-CPU divider.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/6a9169e5bc92c2b9549292769a0814e04b9147cf.1676560357.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index 0f59c84229a8..7e90e94c4b68 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = { DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), /* Core Clock Outputs */ + DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1), DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1), |