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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-09-09 11:25:12 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-09-18 14:43:51 +0200 |
| commit | a4f8a6e60cd54073d27c857cd0c659c5c79cebe2 (patch) | |
| tree | b11b9a8ab787399126a946d1e379b581953280f1 /drivers/clk/renesas | |
| parent | e312ae92077f90d6ccdca05fb6d640bd9624c37c (diff) | |
| download | linux-stable-a4f8a6e60cd54073d27c857cd0c659c5c79cebe2.tar.gz linux-stable-a4f8a6e60cd54073d27c857cd0c659c5c79cebe2.tar.bz2 linux-stable-a4f8a6e60cd54073d27c857cd0c659c5c79cebe2.zip | |
clk: renesas: r8a779g0: Add watchdog clock
Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4H (R8A779G0) SoC.
Extracted from a larger patch in the BSP by Kazuya Mizuguchi.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a012e4449b976efbeaabebb983fa6cfc1b9329d3.1662714852.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a779g0-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 3fc4233b1ead..2afad6171fc3 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -154,6 +154,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER), DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER), DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER), + DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R), }; /* |