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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-14 11:51:58 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-15 09:43:56 +0100 |
| commit | b5f7c6a507718b45be0d71fcf7eaa933ee738a9e (patch) | |
| tree | 7fde50f7f25eb0bb6150224630c035f26e3f64ac /drivers/clk/renesas | |
| parent | 523ed9442b997c39220ee364b07a8773623e3a58 (diff) | |
| download | linux-stable-b5f7c6a507718b45be0d71fcf7eaa933ee738a9e.tar.gz linux-stable-b5f7c6a507718b45be0d71fcf7eaa933ee738a9e.tar.bz2 linux-stable-b5f7c6a507718b45be0d71fcf7eaa933ee738a9e.zip | |
clk: renesas: r8a779g0: Add Z0 clock support
Add support for the Z0 (Cortex-A76 Sub-System) clock on R-Car V4H, based
on the existing support for Z clocks on R-Car Gen4.
Extracted from a patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/75daa1fd8fa7eaef7b8945bb5906c787222c7ac4.1668423063.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a779g0-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 1da48c81d3dd..c6337a408e5e 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -96,6 +96,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1), /* Core Clock Outputs */ + DEF_GEN4_Z("z0", R8A779G0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0), DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1), |