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| author | Sam Protsenko <semen.protsenko@linaro.org> | 2023-11-09 13:09:24 -0600 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-11-16 20:46:03 +0100 |
| commit | d1d53909bb5fbc9bf618ab78515fdbd5d6b691c6 (patch) | |
| tree | e39a0a48f7ebd10765ce2a0055a9fd7dd2e6306b /drivers/clk/samsung/clk-cpu.h | |
| parent | b85ea95d086471afb4ad062012a4d73cd328fa86 (diff) | |
| download | linux-stable-d1d53909bb5fbc9bf618ab78515fdbd5d6b691c6.tar.gz linux-stable-d1d53909bb5fbc9bf618ab78515fdbd5d6b691c6.tar.bz2 linux-stable-d1d53909bb5fbc9bf618ab78515fdbd5d6b691c6.zip | |
clk: samsung: Fix kernel-doc comments
Fix some issues found in kernel-doc comments in Samsung CCF framework.
It makes scripts/kernel-doc happy, which can be checked with:
$ find drivers/clk/samsung/ -name '*.[ch]' -exec \
scripts/kernel-doc -v -none {} \;
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Fixes: ddeac8d968d4 ("clk: samsung: add infrastructure to register cpu clocks")
Fixes: 721c42a351b1 ("clk: samsung: add common clock framework helper functions for Samsung platforms")
Fixes: 3ff6e0d8d64d ("clk: samsung: Add support to register rate_table for samsung plls")
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20231109190925.2066-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk-cpu.h')
| -rw-r--r-- | drivers/clk/samsung/clk-cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index fc9f67a3b22e..103f64193e42 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -11,7 +11,7 @@ #include "clk.h" /** - * struct exynos_cpuclk_data: config data to setup cpu clocks. + * struct exynos_cpuclk_cfg_data: config data to setup cpu clocks. * @prate: frequency of the primary parent clock (in KHz). * @div0: value to be programmed in the div_cpu0 register. * @div1: value to be programmed in the div_cpu1 register. |