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author | Viresh Kumar <viresh.kumar@st.com> | 2012-04-10 09:02:35 +0530 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2012-05-12 21:19:23 +0200 |
commit | 55b8fd4f428501b0f35d62b8313311fd9863c188 (patch) | |
tree | 2c61fe9c307baa73048345adbb11e20e5eeb586e /drivers/clk/spear/clk.c | |
parent | e12ff34402bd3a6cbeab0423012066874bb10f4b (diff) | |
download | linux-stable-55b8fd4f428501b0f35d62b8313311fd9863c188.tar.gz linux-stable-55b8fd4f428501b0f35d62b8313311fd9863c188.tar.bz2 linux-stable-55b8fd4f428501b0f35d62b8313311fd9863c188.zip |
SPEAr: clk: Add VCO-PLL Synthesizer clock
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations
- In normal mode
vco = (2 * M[15:8] * Fin)/N
- In Dithered mode
vco = (2 * M[15:0] * Fin)/(256 * N)
pll_rate = vco/2^p
vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/spear/clk.c')
-rw-r--r-- | drivers/clk/spear/clk.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/clk/spear/clk.c b/drivers/clk/spear/clk.c new file mode 100644 index 000000000000..376d4e5ff326 --- /dev/null +++ b/drivers/clk/spear/clk.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * SPEAr clk - Common routines + */ + +#include <linux/clk-provider.h> +#include <linux/types.h> +#include "clk.h" + +long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, + unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, + int *index) +{ + unsigned long prev_rate, rate = 0; + + for (*index = 0; *index < rtbl_cnt; (*index)++) { + prev_rate = rate; + rate = calc_rate(hw, parent_rate, *index); + if (drate < rate) { + /* previous clock was best */ + if (*index) { + rate = prev_rate; + (*index)--; + } + break; + } + } + + return rate; +} |