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| author | Emil Renner Berthing <kernel@esmil.dk> | 2022-01-26 18:39:52 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-03-10 18:17:33 -0800 |
| commit | 8c373f8c793cc1bb8f708433dcb8343ba078bd17 (patch) | |
| tree | 32384219d316922eba15f3df8416f513dc717bb2 /drivers/clk/starfive/clk-starfive-jh7100.c | |
| parent | 26ad971faa07951179ae6d39f91b6622da4d020c (diff) | |
| download | linux-stable-8c373f8c793cc1bb8f708433dcb8343ba078bd17.tar.gz linux-stable-8c373f8c793cc1bb8f708433dcb8343ba078bd17.tar.bz2 linux-stable-8c373f8c793cc1bb8f708433dcb8343ba078bd17.zip | |
clk: starfive: jh7100: Support more clock types
Unlike the system clocks there are audio clocks that combine both
multiplexer/divider and gate/multiplexer/divider, so add support for
that.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-7-kernel@esmil.dk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/starfive/clk-starfive-jh7100.c')
| -rw-r--r-- | drivers/clk/starfive/clk-starfive-jh7100.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index a6708f9ebf4c..691aeebc7092 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -534,6 +534,27 @@ static const struct clk_ops jh7100_clk_gmux_ops = { .debug_init = jh7100_clk_debug_init, }; +static const struct clk_ops jh7100_clk_mdiv_ops = { + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .get_parent = jh7100_clk_get_parent, + .set_parent = jh7100_clk_set_parent, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops jh7100_clk_gmd_ops = { + .enable = jh7100_clk_enable, + .disable = jh7100_clk_disable, + .is_enabled = jh7100_clk_is_enabled, + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .get_parent = jh7100_clk_get_parent, + .set_parent = jh7100_clk_set_parent, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + static const struct clk_ops jh7100_clk_inv_ops = { .get_phase = jh7100_clk_get_phase, .set_phase = jh7100_clk_set_phase, @@ -543,6 +564,11 @@ static const struct clk_ops jh7100_clk_inv_ops = { const struct clk_ops *starfive_jh7100_clk_ops(u32 max) { if (max & JH7100_CLK_DIV_MASK) { + if (max & JH7100_CLK_MUX_MASK) { + if (max & JH7100_CLK_ENABLE) + return &jh7100_clk_gmd_ops; + return &jh7100_clk_mdiv_ops; + } if (max & JH7100_CLK_ENABLE) return &jh7100_clk_gdiv_ops; if (max == JH7100_CLK_FRAC_MAX) |