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authorChen-Yu Tsai <wens@csie.org>2017-10-12 16:36:59 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-10-13 09:27:06 +0200
commit05d2eaac96d4284b0967cc522ad22f6f23fdf82a (patch)
treeb5f0cdb3f0a033ae2b1fb3667813153077fd5236 /drivers/clk/sunxi-ng/ccu_common.h
parent4cdbc40d64d4b8303a97e29a52862e4d99502beb (diff)
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clk: sunxi-ng: Add sigma-delta modulation support
Sigma-delta modulation is supported for some PLLs. This allows fractional-N multipliers to be used. In reality we don't know how to configure the individual settings for it. However we can copy existing settings from the vendor kernel to support clock rates that cannot be generated from integer factors, but are really desired. The vendor kernel only uses this for the audio PLL clock, and only on the latest chips. This patch adds a new class of clocks, along with helper functions. It is intended to be merged into N-M-factor style clocks as a feature, much like fractional clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_common.h')
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index cadd1a9f93b6..5d684ce77c54 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -24,6 +24,7 @@
#define CCU_FEATURE_ALL_PREDIV BIT(4)
#define CCU_FEATURE_LOCK_REG BIT(5)
#define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6)
+#define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7)
/* MMC timing mode switch bit */
#define CCU_MMC_NEW_TIMING_MODE BIT(30)