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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-02-08 14:17:27 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-02-08 14:17:27 -0800 |
commit | 4ef1a30c6bd2555d4177fc9286df32e9166d58ba (patch) | |
tree | 0ebec2569f8bf099596448539215f1299202cbd7 /drivers/clk/ti | |
parent | 5939224ccdcc9244ab82cdbdc9d21eb019f7db6a (diff) | |
parent | a832eb203ecd34e486bdde0042cf166e687eb227 (diff) | |
download | linux-stable-4ef1a30c6bd2555d4177fc9286df32e9166d58ba.tar.gz linux-stable-4ef1a30c6bd2555d4177fc9286df32e9166d58ba.tar.bz2 linux-stable-4ef1a30c6bd2555d4177fc9286df32e9166d58ba.zip |
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC late updates from Olof Johansson:
"This is some material that we picked up into our tree late, or that
had more complex dependencies on more than one topic branch that makes
sense to keep separately.
- TI support for secure accelerators and hwrng on OMAP4/5
- TI camera changes for dra7 and am437x and SGX improvement due to
better reset control support on am335x, am437x and dra7
- Davinci moves to proper clocksource on DM365, and regulator/audio
improvements for DM365 and DM644x eval boards"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits)
ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem
ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt
ARM: dts: Configure interconnect target module for am437x sgx
ARM: dts: Configure sgx for dra7
ARM: dts: Configure rstctrl reset for am335x SGX
ARM: dts: dra7: Add ti-sysc node for VPE
ARM: dts: dra7: add vpe clkctrl node
ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries
ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries
ARM: dts: am43xx: add support for clkout1 clock
arm: dts: dra76-evm: Add CAL and OV5640 nodes
arm: dtsi: dra76x: Add CAL dtsi node
arm: dts: dra72-evm-common: Add entries for the CSI2 cameras
ARM: dts: DRA72: Add CAL dtsi node
ARM: dts: dra7-l4: Add ti-sysc node for CAM
ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only
ARM: dts: dra7: add cam clkctrl node
ARM: OMAP2+: Drop legacy platform data for omap4 des
ARM: OMAP2+: Drop legacy platform data for omap4 sham
ARM: OMAP2+: Drop legacy platform data for omap4 aes
...
Diffstat (limited to 'drivers/clk/ti')
-rw-r--r-- | drivers/clk/ti/clk-44xx.c | 13 | ||||
-rw-r--r-- | drivers/clk/ti/clk-54xx.c | 13 |
2 files changed, 26 insertions, 0 deletions
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 2b4dab632318..312a20f8ec0e 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -604,6 +604,18 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons { 0 }, }; +static const struct +omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = { + { OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { 0 }, +}; + static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = { { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL }, { 0 }, @@ -691,6 +703,7 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = { { 0x4a009220, omap4_l3_gfx_clkctrl_regs }, { 0x4a009320, omap4_l3_init_clkctrl_regs }, { 0x4a009420, omap4_l4_per_clkctrl_regs }, + { 0x4a0095a0, omap4_l4_secure_clkctrl_regs }, { 0x4a307820, omap4_l4_wkup_clkctrl_regs }, { 0x4a307a20, omap4_emu_sys_clkctrl_regs }, { 0 }, diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 14d98a890c02..92bf2dda95b9 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -301,6 +301,18 @@ static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst { 0 }, }; +static const struct +omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = { + { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "" }, + { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "" }, + { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "" }, + { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "" }, + { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "" }, + { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { 0 }, +}; + static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = { { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, @@ -523,6 +535,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { { 0x4a008d20, omap5_l4cfg_clkctrl_regs }, { 0x4a008e20, omap5_l3instr_clkctrl_regs }, { 0x4a009020, omap5_l4per_clkctrl_regs }, + { 0x4a0091a0, omap5_l4_secure_clkctrl_regs }, { 0x4a009220, omap5_iva_clkctrl_regs }, { 0x4a009420, omap5_dss_clkctrl_regs }, { 0x4a009520, omap5_gpu_clkctrl_regs }, |