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| author | Sean Wang <sean.wang@mediatek.com> | 2018-03-15 15:40:36 +0800 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2018-03-27 15:18:15 +0530 |
| commit | 548c4597e984b79aad8190235d664f1c3a433f94 (patch) | |
| tree | 94d5a3faf9fea79c55cae410d342f6346b1512a3 /drivers/clk/zynq | |
| parent | 33f32c0e1eb710fb9bca647e0e9b439d88961ea9 (diff) | |
| download | linux-stable-548c4597e984b79aad8190235d664f1c3a433f94.tar.gz linux-stable-548c4597e984b79aad8190235d664f1c3a433f94.tar.bz2 linux-stable-548c4597e984b79aad8190235d664f1c3a433f94.zip | |
dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC
MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has
a single ring is dedicated to memory-to-memory transfer through ring based
descriptor management.
Even though there is only one physical ring available inside HSDMA, the
driver can be easily extended to the support of multiple virtual channels
processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/clk/zynq')
0 files changed, 0 insertions, 0 deletions