diff options
| author | Jagadeesh Kona <quic_jkona@quicinc.com> | 2023-05-24 20:22:00 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-05-24 21:47:16 -0700 |
| commit | 34d54e5833db4cfa4d18cc0a4b6f86fe4730a47d (patch) | |
| tree | 4e9a2a61cfc9bcddbef655bb8c8c5b3895d387d5 /drivers/clk | |
| parent | 441fe711be3842552e32fe884bd9f47f170892cb (diff) | |
| download | linux-stable-34d54e5833db4cfa4d18cc0a4b6f86fe4730a47d.tar.gz linux-stable-34d54e5833db4cfa4d18cc0a4b6f86fe4730a47d.tar.bz2 linux-stable-34d54e5833db4cfa4d18cc0a4b6f86fe4730a47d.zip | |
clk: qcom: clk-alpha-pll: Add support to configure PLL_TEST_CTL_U2
The lucid ole pll reuses lucid evo ops but it has an additional test
control register which is required to be programmed, add support to
program the same.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524145203.13153-2-quic_jkona@quicinc.com
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 2 | ||||
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index b9f6535a7ba7..f81c7c561352 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -55,6 +55,7 @@ #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) +#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) @@ -2096,6 +2097,7 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); /* Disable PLL output */ regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index d07b17186b90..6ff0d08eb938 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -125,6 +125,7 @@ struct alpha_pll_config { u32 test_ctl_val; u32 test_ctl_hi_val; u32 test_ctl_hi1_val; + u32 test_ctl_hi2_val; u32 main_output_mask; u32 aux_output_mask; u32 aux2_output_mask; |