diff options
| author | Chris Morgan <macromorgan@hotmail.com> | 2023-10-18 11:18:46 -0500 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2023-11-16 21:25:55 +0100 |
| commit | 48794cd57a67246acc53a3edfdececdbb5b98453 (patch) | |
| tree | 86c8f53953759effe4e1c7f08d3210e08367580c /drivers/clk | |
| parent | b85ea95d086471afb4ad062012a4d73cd328fa86 (diff) | |
| download | linux-stable-48794cd57a67246acc53a3edfdececdbb5b98453.tar.gz linux-stable-48794cd57a67246acc53a3edfdececdbb5b98453.tar.bz2 linux-stable-48794cd57a67246acc53a3edfdececdbb5b98453.zip | |
clk: rockchip: rk3568: Add PLL rate for 115.2MHz
Add support for a PLL rate of 115.2MHz so that the Powkiddy RK2023 panel
can run at a requested 60hz (59.99, close enough).
I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20231018161848.346947-4-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3568.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 16dabe2b9c47..43185668daf6 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -78,6 +78,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), + RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0), RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), |