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author | Stephen Boyd <sboyd@codeaurora.org> | 2016-05-09 16:04:37 -0700 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-05-12 14:48:22 -0700 |
commit | 5707291c6cada6db7344c90a548d02f427bf376c (patch) | |
tree | fd236323284376cc371624db0f810ce06bcdff1b /drivers/clk | |
parent | 98b8525abb7f0d9a5ab942a2e044011d7e635490 (diff) | |
parent | 7e5385dc722258c862f969ab7e67907156ad0e3f (diff) | |
download | linux-stable-5707291c6cada6db7344c90a548d02f427bf376c.tar.gz linux-stable-5707291c6cada6db7344c90a548d02f427bf376c.tar.bz2 linux-stable-5707291c6cada6db7344c90a548d02f427bf376c.zip |
Merge tag 'v4.7-rockchip-clk4' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk updates from Heiko Stuebner:
Another small rk3399 fixup as well as simplifications around
our handling of the General-Register-Files syscon.
* tag 'v4.7-rockchip-clk4' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: drop old_rate calculation on pll rate changes
clk: rockchip: simplify GRF handling in pll clocks
clk: rockchip: lookup General Register Files in rockchip_clk_init
clk: rockchip: fix the rk3399 sdmmc sample / drv name
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 45 | ||||
-rw-r--r-- | drivers/clk/rockchip/clk-rk3399.c | 4 | ||||
-rw-r--r-- | drivers/clk/rockchip/clk.c | 11 | ||||
-rw-r--r-- | drivers/clk/rockchip/clk.h | 1 |
4 files changed, 14 insertions, 47 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 8ac73bc7f93d..db81e454166b 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -92,15 +92,10 @@ static long rockchip_pll_round_rate(struct clk_hw *hw, */ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) { - struct regmap *grf = rockchip_clk_get_grf(pll->ctx); + struct regmap *grf = pll->ctx->grf; unsigned int val; int delay = 24000000, ret; - if (IS_ERR(grf)) { - pr_err("%s: grf regmap not available\n", __func__); - return PTR_ERR(grf); - } - while (delay > 0) { ret = regmap_read(grf, pll->lock_offset, &val); if (ret) { @@ -252,17 +247,9 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); const struct rockchip_pll_rate_table *rate; - unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate); - struct regmap *grf = rockchip_clk_get_grf(pll->ctx); - - if (IS_ERR(grf)) { - pr_debug("%s: grf regmap not available, aborting rate change\n", - __func__); - return PTR_ERR(grf); - } - pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", - __func__, __clk_get_name(hw->clk), old_rate, drate, prate); + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, __clk_get_name(hw->clk), drate, prate); /* Get required rate settings from table */ rate = rockchip_get_pll_settings(pll, drate); @@ -491,17 +478,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); const struct rockchip_pll_rate_table *rate; - unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); - struct regmap *grf = rockchip_clk_get_grf(pll->ctx); - - if (IS_ERR(grf)) { - pr_debug("%s: grf regmap not available, aborting rate change\n", - __func__); - return PTR_ERR(grf); - } - pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", - __func__, clk_hw_get_name(hw), old_rate, drate, prate); + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, clk_hw_get_name(hw), drate, prate); /* Get required rate settings from table */ rate = rockchip_get_pll_settings(pll, drate); @@ -565,11 +544,6 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf || rate->nb != cur.nb) { - struct regmap *grf = rockchip_clk_get_grf(pll->ctx); - - if (IS_ERR(grf)) - return; - pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", __func__, clk_hw_get_name(hw)); rockchip_rk3066_pll_set_params(pll, rate); @@ -749,10 +723,9 @@ static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); const struct rockchip_pll_rate_table *rate; - unsigned long old_rate = rockchip_rk3399_pll_recalc_rate(hw, prate); - pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", - __func__, __clk_get_name(hw->clk), old_rate, drate, prate); + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, __clk_get_name(hw->clk), drate, prate); /* Get required rate settings from table */ rate = rockchip_get_pll_settings(pll, drate); @@ -943,13 +916,13 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, switch (pll_type) { case pll_rk3036: - if (!pll->rate_table) + if (!pll->rate_table || IS_ERR(ctx->grf)) init.ops = &rockchip_rk3036_pll_clk_norate_ops; else init.ops = &rockchip_rk3036_pll_clk_ops; break; case pll_rk3066: - if (!pll->rate_table) + if (!pll->rate_table || IS_ERR(ctx->grf)) init.ops = &rockchip_rk3066_pll_clk_norate_ops; else init.ops = &rockchip_rk3066_pll_clk_ops; diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 5248726af86d..291543f52caa 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -894,8 +894,8 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(6), 1, GFLAGS), - MMC(SCLK_SDMMC_DRV, "emmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), - MMC(SCLK_SDMMC_SAMPLE, "emmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index f0a8be1553b0..7ffd134995f2 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -347,6 +347,9 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np, ctx->grf = ERR_PTR(-EPROBE_DEFER); spin_lock_init(&ctx->lock); + ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, + "rockchip,grf"); + return ctx; err_free: @@ -362,14 +365,6 @@ void __init rockchip_clk_of_add_provider(struct device_node *np, pr_err("%s: could not register clk provider\n", __func__); } -struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx) -{ - if (IS_ERR(ctx->grf)) - ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, - "rockchip,grf"); - return ctx->grf; -} - void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, struct clk *clk, unsigned int id) { diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 1abb7d05d1c7..2194ffa8c9fd 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -600,7 +600,6 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks); void rockchip_clk_of_add_provider(struct device_node *np, struct rockchip_clk_provider *ctx); -struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx); void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, struct clk *clk, unsigned int id); void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, |