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authorIcenowy Zheng <icenowy@aosc.io>2019-03-14 19:21:08 +0800
committerMaxime Ripard <maxime.ripard@bootlin.com>2019-03-18 08:07:21 +0100
commit6630aad719bc0a46dcc4a6732ab783c4c9b80f88 (patch)
tree5dc7bad92780d824727d649d60222487c28b9096 /drivers/clk
parentab65e04dc101d55f1509059725cf9d331141f6e8 (diff)
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clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8. Fix this problem. Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
index a09dfbe36402..dc9f0a365664 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
@@ -240,7 +240,7 @@ static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
- 0x0cc, BIT(8), 0);
+ 0x0cc, BIT(1), 0);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
0x100, BIT(0), 0);