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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-05-13 00:17:21 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-07-31 14:24:04 -0700 |
| commit | 6bab5dab6ed3c2b0eb9112f288ce05276083b492 (patch) | |
| tree | 63eed3fc835fef3ac21a1cf5e846039acc436b2b /drivers/clk | |
| parent | b7fd5d19e32aa65fbbba616e99f4e2deda8405ac (diff) | |
| download | linux-stable-6bab5dab6ed3c2b0eb9112f288ce05276083b492.tar.gz linux-stable-6bab5dab6ed3c2b0eb9112f288ce05276083b492.tar.bz2 linux-stable-6bab5dab6ed3c2b0eb9112f288ce05276083b492.zip | |
clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-5-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/gcc-mdm9615.c | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 8bed02a748ab..fb5c1244fb97 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -207,7 +207,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -258,7 +258,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -309,7 +309,7 @@ static struct clk_rcg gsbi3_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -360,7 +360,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -411,7 +411,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -474,7 +474,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -523,7 +523,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -572,7 +572,7 @@ static struct clk_rcg gsbi3_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -621,7 +621,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -670,7 +670,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -725,7 +725,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_names = gcc_cxo, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -774,7 +774,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_names = gcc_cxo, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -823,7 +823,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_names = gcc_cxo, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -875,7 +875,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -937,7 +937,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, } @@ -985,7 +985,7 @@ static struct clk_rcg sdc2_src = { .hw.init = &(struct clk_init_data){ .name = "sdc2_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1038,7 +1038,7 @@ static struct clk_rcg usb_hs1_xcvr_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1087,7 +1087,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1142,7 +1142,7 @@ static struct clk_rcg usb_hs1_system_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_system_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1197,7 +1197,7 @@ static struct clk_rcg usb_hsic_system_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_system_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1252,7 +1252,7 @@ static struct clk_rcg usb_hsic_hsic_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_hsic_src", .parent_names = gcc_cxo_pll14, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll14), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, |