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authorStephen Boyd <sboyd@kernel.org>2023-12-16 16:28:56 -0800
committerStephen Boyd <sboyd@kernel.org>2023-12-16 16:28:56 -0800
commit723facbbb56048645ab59554801b278c3b7f08b7 (patch)
tree7c9b2a3421ee51e025fb8a0512e4ffb583465008 /drivers/clk
parentb85ea95d086471afb4ad062012a4d73cd328fa86 (diff)
parent721bf080f249ab2adcc4337abe164230bfb8594f (diff)
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Merge tag 'v6.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner: Two new pll rates and an additional critical clock on rk3568. * tag 'v6.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3568: Mark pclk_usb as critical clk: rockchip: rk3568: Add PLL rate for 126.4MHz clk: rockchip: rk3568: Add PLL rate for 115.2MHz
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/rockchip/clk-rk3568.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 16dabe2b9c47..feb9ae484387 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -77,7 +77,9 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
+ RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),
RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
+ RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0),
RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
@@ -1592,6 +1594,7 @@ static const char *const rk3568_cru_critical_clocks[] __initconst = {
"hclk_php",
"pclk_php",
"hclk_usb",
+ "pclk_usb",
"hclk_vo",
};