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| author | Marek Vasut <marek.vasut@gmail.com> | 2017-07-09 15:28:13 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-07-17 11:51:00 -0700 |
| commit | 73100e79c7368dd30c06bcfc04252bab5dc48783 (patch) | |
| tree | 478a2ca153a74a56fe1a794e5e19cb208910e4fa /drivers/clk | |
| parent | 8c1ebe9762670159ca982167131af63c94ff1571 (diff) | |
| download | linux-stable-73100e79c7368dd30c06bcfc04252bab5dc48783.tar.gz linux-stable-73100e79c7368dd30c06bcfc04252bab5dc48783.tar.bz2 linux-stable-73100e79c7368dd30c06bcfc04252bab5dc48783.zip | |
clk: vc5: Add bindings for IDT VersaClock 5P49V6901
IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either external crystal or from
external reference clock.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
0 files changed, 0 insertions, 0 deletions