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author | Shawn Lin <shawn.lin@rock-chips.com> | 2018-03-08 14:49:41 +0800 |
---|---|---|
committer | Michael Turquette <mturquette@baylibre.com> | 2018-03-11 18:21:19 -0700 |
commit | 7f95beea36089918335eb1810ddd7ba8cf9d09cc (patch) | |
tree | b47461069098a6da89d660de586ff96fc00c47ed /drivers/clk | |
parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
download | linux-stable-7f95beea36089918335eb1810ddd7ba8cf9d09cc.tar.gz linux-stable-7f95beea36089918335eb1810ddd7ba8cf9d09cc.tar.bz2 linux-stable-7f95beea36089918335eb1810ddd7ba8cf9d09cc.zip |
clk: update cached phase to respect the fact when setting phase
It's found that the final phase set by driver doesn't match that of
the output from clk_summary:
dwmmc_rockchip fe310000.dwmmc: Successfully tuned phase to 346
mmc0: new ultra high speed SDR104 SDIO card at address 0001
cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample
sdio_sample 0 1 0 50000000 0 0
It seems the cached core->phase isn't updated after the clk was
registered. So fix this issue by updating the core->phase if setting
phase successfully.
Fixes: 9e4d04adeb1a ("clk: add clk_core_set_phase_nolock function")
Cc: Stable <stable@vger.kernel.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/clk.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 0f686a9dac3e..617e56268b18 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2309,8 +2309,11 @@ static int clk_core_set_phase_nolock(struct clk_core *core, int degrees) trace_clk_set_phase(core, degrees); - if (core->ops->set_phase) + if (core->ops->set_phase) { ret = core->ops->set_phase(core->hw, degrees); + if (!ret) + core->phase = degrees; + } trace_clk_set_phase_complete(core, degrees); |