diff options
author | Dinh Nguyen <dinguyen@kernel.org> | 2021-03-02 15:41:50 -0600 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2021-03-30 19:26:26 -0700 |
commit | 8c489216c3e103a24856fd676fc5f51619c2e052 (patch) | |
tree | d18847f00d12685742da45529ff5325c269d6172 /drivers/clk | |
parent | 2c2b9c6067170de2a63e7e3d9f5bb205b870de7c (diff) | |
download | linux-stable-8c489216c3e103a24856fd676fc5f51619c2e052.tar.gz linux-stable-8c489216c3e103a24856fd676fc5f51619c2e052.tar.bz2 linux-stable-8c489216c3e103a24856fd676fc5f51619c2e052.zip |
clk: socfpga: arria10: convert to use clk_hw
As recommended by Stephen Boyd, convert the Arria10 clock driver to use
the clk_hw registration method.
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210302214151.1333447-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/socfpga/clk-gate-a10.c | 8 | ||||
-rw-r--r-- | drivers/clk/socfpga/clk-periph-a10.c | 11 | ||||
-rw-r--r-- | drivers/clk/socfpga/clk-pll-a10.c | 12 |
3 files changed, 16 insertions, 15 deletions
diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index cd5df9103614..f5cba8298712 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -98,7 +98,7 @@ static void __init __socfpga_gate_init(struct device_node *node, u32 div_reg[3]; u32 clk_phase[2]; u32 fixed_div; - struct clk *clk; + struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; @@ -159,13 +159,13 @@ static void __init __socfpga_gate_init(struct device_node *node, init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); init.parent_names = parent_name; socfpga_clk->hw.hw.init = &init; + hw_clk = &socfpga_clk->hw.hw; - clk = clk_register(NULL, &socfpga_clk->hw.hw); - if (WARN_ON(IS_ERR(clk))) { + if (clk_hw_register(NULL, hw_clk)) { kfree(socfpga_clk); return; } - rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); + rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); if (WARN_ON(rc)) return; } diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c index 3e0c55727b89..b9cdde4b8441 100644 --- a/drivers/clk/socfpga/clk-periph-a10.c +++ b/drivers/clk/socfpga/clk-periph-a10.c @@ -61,7 +61,7 @@ static __init void __socfpga_periph_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; @@ -104,12 +104,13 @@ static __init void __socfpga_periph_init(struct device_node *node, periph_clk->hw.hw.init = &init; - clk = clk_register(NULL, &periph_clk->hw.hw); - if (WARN_ON(IS_ERR(clk))) { + hw_clk = &periph_clk->hw.hw; + + if (clk_hw_register(NULL, hw_clk)) { kfree(periph_clk); return; } - rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); + rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); if (rc < 0) { pr_err("Could not register clock provider for node:%s\n", clk_name); @@ -119,7 +120,7 @@ static __init void __socfpga_periph_init(struct device_node *node, return; err_clk: - clk_unregister(clk); + clk_hw_unregister(hw_clk); } void __init socfpga_a10_periph_init(struct device_node *node) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 3338f054fe98..bee0f7da5b6e 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -63,11 +63,11 @@ static const struct clk_ops clk_pll_ops = { .get_parent = clk_pll_get_parent, }; -static struct clk * __init __socfpga_pll_init(struct device_node *node, +static struct clk_hw * __init __socfpga_pll_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; - struct clk *clk; + struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFGPA_MAX_PARENTS]; @@ -101,14 +101,14 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; + hw_clk = &pll_clk->hw.hw; - clk = clk_register(NULL, &pll_clk->hw.hw); - if (WARN_ON(IS_ERR(clk))) { + if (clk_hw_register(NULL, hw_clk)) { kfree(pll_clk); return NULL; } - of_clk_add_provider(node, of_clk_src_simple_get, clk); - return clk; + of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); + return hw_clk; } void __init socfpga_a10_pll_init(struct device_node *node) |