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| author | Heiko Stuebner <heiko@sntech.de> | 2018-11-15 12:17:30 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-12-13 08:51:18 +0100 |
| commit | e9ad6c940e1b1358615b9b2acd49ed9d7c6622af (patch) | |
| tree | efa64c91bb3628722ffbef0fa809813b750dc3b2 /drivers/clk | |
| parent | d499bc748dbb805dcbb75d8436e0f5ec944475d3 (diff) | |
| download | linux-stable-e9ad6c940e1b1358615b9b2acd49ed9d7c6622af.tar.gz linux-stable-e9ad6c940e1b1358615b9b2acd49ed9d7c6622af.tar.bz2 linux-stable-e9ad6c940e1b1358615b9b2acd49ed9d7c6622af.zip | |
clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
[ Upstream commit ac8cb53829a6ba119082e067f5bc8fab3611ce6a ]
Similar to commit a9f0c0e56371 ("clk: rockchip: fix rk3188 sclk_smc
gate data") there is one other gate clock in the rk3188 clock driver
with a similar wrong ordering, the sclk_mac_lbtest. So fix it as well.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3188.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 9a6ad5a4cdf0..2ca7e2be2f09 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -362,8 +362,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKGATE_CON(2), 5, GFLAGS), MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 4, 1, MFLAGS), - GATE(0, "sclk_mac_lbtest", "sclk_macref", - RK2928_CLKGATE_CON(2), 12, 0, GFLAGS), + GATE(0, "sclk_mac_lbtest", "sclk_macref", 0, + RK2928_CLKGATE_CON(2), 12, GFLAGS), COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, |