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authorTony W Wang-oc <TonyWWang-oc@zhaoxin.com>2022-06-23 09:21:26 +0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2022-06-29 20:14:39 +0200
commitd6f895965592d5cd2771860639219964df85d555 (patch)
treec7caa3a36b26e73b0f5f42600373a152114e5109 /drivers/cpufreq
parent9ab9b9d3fb9231cdcfda8e0fb3d9c24a2f95ed26 (diff)
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cpufreq: ACPI: Add Zhaoxin/Centaur turbo boost control interface support
Recent Zhaoxin/Centaur CPUs support X86_FEATURE_IDA and the turbo boost can be dynamically enabled or disabled through MSR 0x1a0[38] in the same way as Intel. So add turbo boost control support for these CPUs too. Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/cpufreq')
-rw-r--r--drivers/cpufreq/acpi-cpufreq.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 3d514b82d055..1bb2b90ebb21 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -78,6 +78,8 @@ static bool boost_state(unsigned int cpu)
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_INTEL:
+ case X86_VENDOR_CENTAUR:
+ case X86_VENDOR_ZHAOXIN:
rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi);
msr = lo | ((u64)hi << 32);
return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
@@ -97,6 +99,8 @@ static int boost_set_msr(bool enable)
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_INTEL:
+ case X86_VENDOR_CENTAUR:
+ case X86_VENDOR_ZHAOXIN:
msr_addr = MSR_IA32_MISC_ENABLE;
msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
break;