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| author | Wojciech Ziemba <wojciech.ziemba@intel.com> | 2021-04-09 14:56:19 +0100 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2021-04-16 21:16:34 +1000 |
| commit | 1c4d9d5bbb5a94ff51853be1089dd48546d4f81c (patch) | |
| tree | 1775603a6d988dc1ebb0a1a643b3a2c7bf617648 /drivers/crypto/qat/qat_c3xxx | |
| parent | 7e958d301c0db051c358001d818c8b8637131190 (diff) | |
| download | linux-stable-1c4d9d5bbb5a94ff51853be1089dd48546d4f81c.tar.gz linux-stable-1c4d9d5bbb5a94ff51853be1089dd48546d4f81c.tar.bz2 linux-stable-1c4d9d5bbb5a94ff51853be1089dd48546d4f81c.zip | |
crypto: qat - enable detection of accelerators hang
Enable the detection of hangs by setting watchdog timers (WDTs) on
generations that supports that feature.
The default timeout value comes from HW specs. WTDs are reset each time
an accelerator wins arbitration and is able to send/read a command to/from
an accelerator.
The value has added significant margin to make sure there are no spurious
timeouts. The scope of watchdog is per QAT device.
If a timeout is detected, the firmware resets the accelerator and
returns a response descriptor with an appropriate error code.
Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/qat/qat_c3xxx')
| -rw-r--r-- | drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c index f5990d042c9a..1dd64af22bea 100644 --- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c +++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c @@ -212,6 +212,7 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data) hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms; hw_data->reset_device = adf_reset_flr; hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION; + hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer; adf_gen2_init_hw_csr_ops(&hw_data->csr_ops); } |