diff options
| author | Muralidhara M K <muralidhara.mk@amd.com> | 2023-01-27 17:04:10 +0000 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2023-03-24 13:03:20 +0100 |
| commit | b29dad9bf3ce13e7a37f7fc75ee2c95ac48b9f08 (patch) | |
| tree | 6b6980e32fd5f8d8e61533fe671987e75ffbb0f7 /drivers/edac | |
| parent | 637f60ef2cc7c015c2e065503f8da89272ab208d (diff) | |
| download | linux-stable-b29dad9bf3ce13e7a37f7fc75ee2c95ac48b9f08.tar.gz linux-stable-b29dad9bf3ce13e7a37f7fc75ee2c95ac48b9f08.tar.bz2 linux-stable-b29dad9bf3ce13e7a37f7fc75ee2c95ac48b9f08.zip | |
EDAC/amd64: Split read_base_mask() into dct/umc functions
Call them from their respective hw_info_get() paths.
Call the new functions after the setting the chip select base and mask
counts, since those are need to read the correct number of chip select
base and mask registers. And call the new functions before the remaining
set up, because the base and mask register values will be needed later.
[Yazen: Rebased/reworked patch and reworded commit message. ]
Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com>
Co-developed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Co-developed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127170419.1824692-14-yazen.ghannam@amd.com
Diffstat (limited to 'drivers/edac')
| -rw-r--r-- | drivers/edac/amd64_edac.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 0ba63c93f8f4..0729ce10e483 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1638,7 +1638,7 @@ static void umc_prep_chip_selects(struct amd64_pvt *pvt) } } -static void read_umc_base_mask(struct amd64_pvt *pvt) +static void umc_read_base_mask(struct amd64_pvt *pvt) { u32 umc_base_reg, umc_base_reg_sec; u32 umc_mask_reg, umc_mask_reg_sec; @@ -1692,13 +1692,10 @@ static void read_umc_base_mask(struct amd64_pvt *pvt) /* * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers */ -static void read_dct_base_mask(struct amd64_pvt *pvt) +static void dct_read_base_mask(struct amd64_pvt *pvt) { int cs; - if (pvt->umc) - return read_umc_base_mask(pvt); - for_each_chip_select(cs, 0, pvt) { int reg0 = DCSB0 + (cs * 4); int reg1 = DCSB1 + (cs * 4); @@ -3185,7 +3182,6 @@ static void read_mc_regs(struct amd64_pvt *pvt) } skip: - read_dct_base_mask(pvt); determine_memory_type(pvt); @@ -3666,6 +3662,7 @@ static int dct_hw_info_get(struct amd64_pvt *pvt) return ret; dct_prep_chip_selects(pvt); + dct_read_base_mask(pvt); read_mc_regs(pvt); return 0; @@ -3678,6 +3675,7 @@ static int umc_hw_info_get(struct amd64_pvt *pvt) return -ENOMEM; umc_prep_chip_selects(pvt); + umc_read_base_mask(pvt); read_mc_regs(pvt); return 0; |