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| author | Shirish S <shirish.s@amd.com> | 2019-07-16 14:49:48 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-30 23:23:12 -0500 |
| commit | 1c4259159132ae4ceaf7c6db37a6cf76417f73d9 (patch) | |
| tree | 4ac51006ca277702bbfd3bb3b01333a08afea36f /drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | |
| parent | ddcb7fc62f4be99faedfa1764c971a2f31468962 (diff) | |
| download | linux-stable-1c4259159132ae4ceaf7c6db37a6cf76417f73d9.tar.gz linux-stable-1c4259159132ae4ceaf7c6db37a6cf76417f73d9.tar.bz2 linux-stable-1c4259159132ae4ceaf7c6db37a6cf76417f73d9.zip | |
drm/amd/display: enable S/G for RAVEN chip
enables gpu_vm_support in dm and adds
AMDGPU_GEM_DOMAIN_GTT as supported domain
v2:
Move BO placement logic into amdgpu_display_supported_domains
v3:
Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains.
v4:
amdgpu_bo_validate_uswc moved to sepperate patch.
Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_display.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index ddd8f5b0f2d3..8b06150080aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -507,7 +507,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev) * APUs. So force the BO placement to VRAM in case this architecture * will not allow USWC mappings. */ - if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && + if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN && adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) && amdgpu_device_asic_has_dc_support(adev->asic_type)) domain |= AMDGPU_GEM_DOMAIN_GTT; |