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author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-03-30 11:52:33 -0700 |
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committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-03-30 11:52:33 -0700 |
commit | 1f901d59a5489e4dc7fdd339808d89b89f35483e (patch) | |
tree | a43fd6c318a8f2af763ae8186af8ecde49cad582 /drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | |
parent | 4df4925b1b26f285aa76f89d95db3388a2d55281 (diff) | |
parent | 694f54f680f7fd8e9561928fbfc537d9afbc3d79 (diff) | |
download | linux-stable-1f901d59a5489e4dc7fdd339808d89b89f35483e.tar.gz linux-stable-1f901d59a5489e4dc7fdd339808d89b89f35483e.tar.bz2 linux-stable-1f901d59a5489e4dc7fdd339808d89b89f35483e.zip |
Merge airlied/drm-next into drm-intel-next-queued
Commit 'aee3bac0a3a8 ("drm/i915/psr: Tie PSR2 support to Y
coordinate requirement")' got merged to drm-intel-next-queued
but the variable was defined commit 'c5fe47327b06 ("drm: Add PSR
version 3 macro") who was merged through drm-misc.
So backmerging to get drm-intel-next-queued compiling back again.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c index 8ce74a1d9966..4b584cb75bf4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c @@ -105,14 +105,25 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, int ret; ww_mutex_lock(&resv->lock, NULL); - ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE, false, - AMDGPU_GEM_DOMAIN_GTT, 0, sg, resv, &bo); - ww_mutex_unlock(&resv->lock); + ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_CPU, 0, ttm_bo_type_sg, + resv, &bo); if (ret) - return ERR_PTR(ret); + goto error; - bo->prime_shared_count = 1; + bo->tbo.sg = sg; + bo->tbo.ttm->sg = sg; + bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; + if (attach->dmabuf->ops != &amdgpu_dmabuf_ops) + bo->prime_shared_count = 1; + + ww_mutex_unlock(&resv->lock); return &bo->gem_base; + +error: + ww_mutex_unlock(&resv->lock); + return ERR_PTR(ret); } static int amdgpu_gem_map_attach(struct dma_buf *dma_buf, @@ -121,6 +132,7 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf, { struct drm_gem_object *obj = dma_buf->priv; struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); long r; r = drm_gem_map_attach(dma_buf, target_dev, attach); @@ -132,7 +144,7 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf, goto error_detach; - if (dma_buf->ops != &amdgpu_dmabuf_ops) { + if (attach->dev->driver != adev->dev->driver) { /* * Wait for all shared fences to complete before we switch to future * use of exclusive fence on this prime shared bo. @@ -151,7 +163,7 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf, if (r) goto error_unreserve; - if (dma_buf->ops != &amdgpu_dmabuf_ops) + if (attach->dev->driver != adev->dev->driver) bo->prime_shared_count++; error_unreserve: @@ -168,6 +180,7 @@ static void amdgpu_gem_map_detach(struct dma_buf *dma_buf, { struct drm_gem_object *obj = dma_buf->priv; struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); int ret = 0; ret = amdgpu_bo_reserve(bo, true); @@ -175,7 +188,7 @@ static void amdgpu_gem_map_detach(struct dma_buf *dma_buf, goto error; amdgpu_bo_unpin(bo); - if (dma_buf->ops != &amdgpu_dmabuf_ops && bo->prime_shared_count) + if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count) bo->prime_shared_count--; amdgpu_bo_unreserve(bo); |