diff options
| author | Likun Gao <Likun.Gao@amd.com> | 2022-07-08 11:14:05 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-07-13 11:25:17 -0400 |
| commit | f1549c09c520877be211d483d3c6f4e7f77d2588 (patch) | |
| tree | 166e4b6e8a2e9f6e7059e62b913ebb2b43c0be4e /drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | |
| parent | 58e969b60db0f5ca9abf0a8df28086efd601f38c (diff) | |
| download | linux-stable-f1549c09c520877be211d483d3c6f4e7f77d2588.tar.gz linux-stable-f1549c09c520877be211d483d3c6f4e7f77d2588.tar.bz2 linux-stable-f1549c09c520877be211d483d3c6f4e7f77d2588.zip | |
drm/amdgpu: support reset flag set for gpu reset
Move reset_context out of gpu recover function to make it configurable
for different reset purpose.
For the reset way of call gpu_recovery sysfs, force to use full reset
method. Otherwise, try soft reset by default if the related ASIC
supportted, if soft reset failed, will use full reset.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index c5016a926331..288c414babdf 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -522,8 +522,16 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - if (amdgpu_device_should_recover_gpu(adev)) - amdgpu_device_gpu_recover(adev, NULL); + if (amdgpu_device_should_recover_gpu(adev)) { + struct amdgpu_reset_context reset_context; + memset(&reset_context, 0, sizeof(reset_context)); + + reset_context.method = AMD_RESET_METHOD_NONE; + reset_context.reset_req_dev = adev; + clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); + + amdgpu_device_gpu_recover(adev, NULL, &reset_context); + } } static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, |