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| author | Huang Rui <ray.huang@amd.com> | 2020-08-27 11:05:50 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-05 15:15:27 -0400 |
| commit | 54c98eacf3b93f6b8dad7c042e06ce9971663fb7 (patch) | |
| tree | ecf0e86bc531e99149477ca78178a05ebf15be5e /drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | |
| parent | 1ec743ac9ffe774fc3e9ef7943fb7a60dd8e67ab (diff) | |
| download | linux-stable-54c98eacf3b93f6b8dad7c042e06ce9971663fb7.tar.gz linux-stable-54c98eacf3b93f6b8dad7c042e06ce9971663fb7.tar.bz2 linux-stable-54c98eacf3b93f6b8dad7c042e06ce9971663fb7.zip | |
drm/amdgpu: add sdma support for van gogh
This patch adds the sdma v5.2 support for van gogh.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 9f3952723c63..100d0a921ede 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -47,6 +47,8 @@ MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); +MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); + #define SDMA1_REG_OFFSET 0x600 #define SDMA3_REG_OFFSET 0x400 #define SDMA0_HYP_DEC_REG_START 0x5880 @@ -87,6 +89,7 @@ static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: + case CHIP_VANGOGH: break; default: break; @@ -160,6 +163,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: chip_name = "navy_flounder"; break; + case CHIP_VANGOGH: + chip_name = "vangogh"; + break; default: BUG(); } @@ -1171,6 +1177,9 @@ static int sdma_v5_2_early_init(void *handle) case CHIP_NAVY_FLOUNDER: adev->sdma.num_instances = 2; break; + case CHIP_VANGOGH: + adev->sdma.num_instances = 1; + break; default: break; } @@ -1567,6 +1576,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle, switch (adev->asic_type) { case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: + case CHIP_VANGOGH: sdma_v5_2_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); sdma_v5_2_update_medium_grain_light_sleep(adev, |