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| author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2021-05-05 03:27:49 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-05-10 18:06:45 -0400 |
| commit | bcfbb6016b3d732d71130db3489888583f692386 (patch) | |
| tree | 94005657f428f01bc77034aebeaf155655e09fec /drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | |
| parent | 67387dfe0f6630f2d4f412ce77debec23a49db7a (diff) | |
| download | linux-stable-bcfbb6016b3d732d71130db3489888583f692386.tar.gz linux-stable-bcfbb6016b3d732d71130db3489888583f692386.tar.bz2 linux-stable-bcfbb6016b3d732d71130db3489888583f692386.zip | |
drm/amdgpu: Init GFX10_ADDR_CONFIG for VCN v3 in DPG mode.
Otherwise tiling modes that require the values form this field
(In particular _*_X) would be corrupted upon video decode.
Copied from the VCN v2 code.
Fixes: 99541f392b4d ("drm/amdgpu: add mc resume DPG mode for VCN3.0")
Reviewed-and-Tested by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 3f15bf34123a..cf165ab5dd26 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -589,6 +589,10 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); + + /* VCN global tiling registers */ + WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( + UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); } static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) |