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| author | Hansen Dsouza <Hansen.Dsouza@amd.com> | 2022-01-26 15:44:50 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-02-17 15:58:45 -0500 |
| commit | c477eaa6a79da6af7e59f74e69af7d6b3af52a23 (patch) | |
| tree | 2028998eddc7000219ae7c9e5dff15b73f9b1daf /drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | |
| parent | 868f4357ed0d1e2f96bbd67d4ac862aa6335effe (diff) | |
| download | linux-stable-c477eaa6a79da6af7e59f74e69af7d6b3af52a23.tar.gz linux-stable-c477eaa6a79da6af7e59f74e69af7d6b3af52a23.tar.bz2 linux-stable-c477eaa6a79da6af7e59f74e69af7d6b3af52a23.zip | |
drm/amd/display: Add DCN316 resource and SMU clock manager
Add core DC implementation for DCN316.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index a707d07d5197..0a608bd4bd61 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -43,6 +43,7 @@ #include "dcn30/dcn30_clk_mgr.h" #include "dcn301/vg_clk_mgr.h" #include "dcn31/dcn31_clk_mgr.h" +#include "dcn316/dcn316_clk_mgr.h" int clk_mgr_helper_get_active_display_cnt( @@ -278,8 +279,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p return &clk_mgr->base.base; } break; - case FAMILY_YELLOW_CARP: - case AMDGPU_FAMILY_GC_10_3_7:{ + case FAMILY_YELLOW_CARP: { struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); if (clk_mgr == NULL) { @@ -290,6 +290,17 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base.base; } + case AMDGPU_FAMILY_GC_10_3_7: { + struct clk_mgr_dcn316 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); + + if (clk_mgr == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base.base; + } #endif default: @@ -323,10 +334,13 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) break; case FAMILY_YELLOW_CARP: - case AMDGPU_FAMILY_GC_10_3_7: dcn31_clk_mgr_destroy(clk_mgr); break; + case AMDGPU_FAMILY_GC_10_3_7: + dcn316_clk_mgr_destroy(clk_mgr); + break; + default: break; } |