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author | Saaem Rizvi <SyedSaaem.Rizvi@amd.com> | 2022-06-09 15:34:43 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-21 18:17:23 -0400 |
commit | 4b33b5ffcf68de3a43e7dddc91c5dc86e6ed8587 (patch) | |
tree | 609fe2126964cf4ebe67147272191523c3e23b0f /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301 | |
parent | 3ab55e3a1ebc22c1e0b7c72261a8c9fe78a3a09a (diff) | |
download | linux-stable-4b33b5ffcf68de3a43e7dddc91c5dc86e6ed8587.tar.gz linux-stable-4b33b5ffcf68de3a43e7dddc91c5dc86e6ed8587.tar.bz2 linux-stable-4b33b5ffcf68de3a43e7dddc91c5dc86e6ed8587.zip |
drm/amd/display: Add SMU logging code
[WHY]
Logging for SMU response value after the wait allows us to know
immediately what the response value was. Makes it easier to debug should
the value be anything other than OK.
[HOW]
Using the the already available DC SMU logging functions.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c index 1cae01a91a69..d8f03328558b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c @@ -41,6 +41,12 @@ #define FN(reg_name, field) \ FD(reg_name##__##field) +#include "logger_types.h" +#undef DC_LOGGER +#define DC_LOGGER \ + CTX->logger +#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } + #define VBIOSSMC_MSG_GetSmuVersion 0x2 #define VBIOSSMC_MSG_SetDispclkFreq 0x4 #define VBIOSSMC_MSG_SetDprefclkFreq 0x5 @@ -96,6 +102,12 @@ static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000); + smu_print("SMU response after wait: %d\n", result); + + if (result == VBIOSSMC_Status_BUSY) { + return -1; + } + /* First clear response register */ REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); |