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| author | Charlene Liu <charlene.liu@amd.com> | 2023-08-16 20:40:57 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-09-20 16:24:08 -0400 |
| commit | 4f43d753bf9c709ff771eb6dff76269e657555a6 (patch) | |
| tree | fbb23c86bb83835f9e414d527a875497ac95aa00 /drivers/gpu/drm/amd/display/dc/clk_mgr | |
| parent | 990d988847c469b5e1e5e0748fb02ef613d9e0d1 (diff) | |
| download | linux-stable-4f43d753bf9c709ff771eb6dff76269e657555a6.tar.gz linux-stable-4f43d753bf9c709ff771eb6dff76269e657555a6.tar.bz2 linux-stable-4f43d753bf9c709ff771eb6dff76269e657555a6.zip | |
drm/amd/display: Correct z8 watermark mask
Correct z8_watermark mask from 16bit to 20bit. Also, do not set dcn35
dprefclk in clk_mgr_construct.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index ca6ce13921a7..b258eb37a859 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -930,8 +930,6 @@ void dcn35_clk_mgr_construct( /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/ dcn35_read_ss_info_from_lut(&clk_mgr->base); - clk_mgr->base.base.dprefclk_khz = - dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz); clk_mgr->base.base.bw_params = &dcn35_bw_params; |