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| author | Jun Lei <Jun.Lei@amd.com> | 2019-10-03 15:09:53 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-10-25 16:50:09 -0400 |
| commit | 0460f9abf275ef3cdab4c531bfa06e2552f5e1c3 (patch) | |
| tree | 936f55105900cb0acfaa8d9dd333a2beea4068b7 /drivers/gpu/drm/amd/display/dc/core | |
| parent | e9c93e5af395022eb52923ae84e29b9b0b6d7073 (diff) | |
| download | linux-stable-0460f9abf275ef3cdab4c531bfa06e2552f5e1c3.tar.gz linux-stable-0460f9abf275ef3cdab4c531bfa06e2552f5e1c3.tar.bz2 linux-stable-0460f9abf275ef3cdab4c531bfa06e2552f5e1c3.zip | |
drm/amd/display: do not synchronize "drr" displays
[why]
A display that supports DRR can never really be considered
"synchronized" with any other display because we can dynamically
enable DRR (i.e. without modeset). this will cause their
relative CRTC positions to drift and lose sync. this will disrupt
features such as MCLK switching that assume and depend on
their permanent alignment (that can only change with modeset)
[how]
check for ignore_msa in stream when considered synchronizability
this ignore_msa is basically actually implemented as "supports drr"
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index da9e2e5f5c0d..8fe39fdefc27 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -404,6 +404,9 @@ bool resource_are_streams_timing_synchronizable( if (stream1->view_format != stream2->view_format) return false; + if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) + return false; + return true; } static bool is_dp_and_hdmi_sharable( @@ -1540,6 +1543,9 @@ bool dc_is_stream_unchanged( if (!are_stream_backends_same(old_stream, stream)) return false; + if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) + return false; + return true; } |