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| author | Martin Leung <Martin.Leung@amd.com> | 2021-12-10 15:04:07 -0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-12-14 16:08:41 -0500 |
| commit | 4866b0bfea40cddb7275c88aeb95b47dac3d2a35 (patch) | |
| tree | ddb844499963c8b30b11cb3f3d8cfb12cfb9d496 /drivers/gpu/drm/amd/display/dc/dc.h | |
| parent | b477143566d5b16c8b92ffec2cb3a896fe818509 (diff) | |
| download | linux-stable-4866b0bfea40cddb7275c88aeb95b47dac3d2a35.tar.gz linux-stable-4866b0bfea40cddb7275c88aeb95b47dac3d2a35.tar.bz2 linux-stable-4866b0bfea40cddb7275c88aeb95b47dac3d2a35.zip | |
drm/amd/display: implement dc_mode_memclk
why:
Need interface to lower clocks when in dc (power save)
mode. Must be able to work with p_state unsupported cases
Can cause flicker when OS notifies us of dc state change
how:
added dal3 interface for KMD
added pathway to query smu for this softmax
added blank before clock change to override underflow
added logic to change clk based on pstatesupport and softmax
added logic in prepare/optimize_bw to conform while changing
clocks
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Martin Leung <Martin.Leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a43c008bd0f2..963b58803ae5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1432,6 +1432,9 @@ void dc_unlock_memory_clock_frequency(struct dc *dc); */ void dc_lock_memory_clock_frequency(struct dc *dc); +/* set soft max for memclk, to be used for AC/DC switching clock limitations */ +void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); + /* cleanup on driver unload */ void dc_hardware_release(struct dc *dc); |