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author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2023-05-12 14:03:15 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2023-08-07 17:12:49 -0400 |
commit | e013864479f7572153b27072b6693d45301e3cf6 (patch) | |
tree | efd18e990aca47c766fe399d8c5096a0f3a6abbd /drivers/gpu/drm/amd/display/dc/dc.h | |
parent | e2e42edfe8533af7b30f505d41d44e0d180065da (diff) | |
download | linux-stable-e013864479f7572153b27072b6693d45301e3cf6.tar.gz linux-stable-e013864479f7572153b27072b6693d45301e3cf6.tar.bz2 linux-stable-e013864479f7572153b27072b6693d45301e3cf6.zip |
drm/amd/display: Add structs for Freesync Panel Replay
In some instances, the GPU is transmitting repeated frame to the sink
without any updates or changes in the content. These repeat transmission
are wasteful, resulting in power draw in different aspects of the system
1. DCN is fetching the frame of data from DF/UMC/DRAM. This memory traffic
prevents power down of parts of this HW path.
2. GPU is transmitting pixel data to the display through the main link of
the DisplayPort interface. This prevents power down of both the Source
transmitter (TX) and the Sink receiver (RX)
The concepts of utilizing replay is similar to PSR, but there is a benefit of:
Source and Sink remaining synchronized which allows for
- lower latency when switching from replay to live frames
- enable the possibility of more use cases
- easy control of the sink's refresh rate during replay
Due to Source and Sink remaining timing synchronized, Replay can be activated
in more UI scenarios.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index eadb53853131..d16e310e46a5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -430,6 +430,7 @@ enum visual_confirm { VISUAL_CONFIRM_SWAPCHAIN = 6, VISUAL_CONFIRM_FAMS = 7, VISUAL_CONFIRM_SWIZZLE = 9, + VISUAL_CONFIRM_REPLAY = 12, VISUAL_CONFIRM_SUBVP = 14, VISUAL_CONFIRM_MCLK_SWITCH = 16, }; @@ -905,6 +906,7 @@ struct dc_debug_options { uint32_t fpo_vactive_max_blank_us; bool enable_legacy_fast_update; bool disable_dc_mode_overwrite; + bool replay_skip_crtc_disabled; }; struct gpu_info_soc_bounding_box_v1_0; @@ -1524,6 +1526,8 @@ struct dc_link { struct backlight_settings backlight_settings; struct psr_settings psr_settings; + struct replay_settings replay_settings; + /* Drive settings read from integrated info table */ struct dc_lane_settings bios_forced_drive_settings; |