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| author | Harry Wentland <harry.wentland@amd.com> | 2019-02-25 13:26:34 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:07 -0500 |
| commit | 97bda0322b8a91aa8d534763e709571b2334e585 (patch) | |
| tree | 9e572c249b54a91c58a771d5eeef5ffc51cfe587 /drivers/gpu/drm/amd/display/dc/dc_dp_types.h | |
| parent | b4f199c7b00c87183f10c0a8f635f26ba2ede3eb (diff) | |
| download | linux-stable-97bda0322b8a91aa8d534763e709571b2334e585.tar.gz linux-stable-97bda0322b8a91aa8d534763e709571b2334e585.tar.bz2 linux-stable-97bda0322b8a91aa8d534763e709571b2334e585.zip | |
drm/amd/display: Add DSC support for Navi (v2)
Add support for DCN2 DSC (Display Stream Compression)
HW Blocks:
+--------++------+ +----------+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+--------++------+ +----------+
| ^
v |
+--------+ +--------+
| DPP | | DWB |
+--------+ +--------+
|
v ^
+--------+ |
| MPC | |
+--------+ |
| |
v |
+-------+ +-------+ |
| OPP | <--> | DSC | |
+-------+ +-------+ |
| |
v |
+--------+ /
| OPTC | --------------
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
v2: rebase (Alex)
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_dp_types.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 11c68a399267..6892bf80c9e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -512,4 +512,18 @@ union test_misc { unsigned char raw; }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +/* FEC capability DPCD register field bits-*/ +union fec_capability { + struct { + uint8_t FEC_CAPABLE:1; + uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; + uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; + uint8_t BIT_ERROR_COUNT_CAPABLE:1; + uint8_t RESERVED:4; + } bits; + uint8_t raw; +}; +#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ + #endif /* DC_DP_TYPES_H */ |