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| author | Wenjing Liu <wenjing.liu@amd.com> | 2021-10-15 12:48:41 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-11-03 12:32:34 -0400 |
| commit | edcf52caa985c010d0a6022190c8e3d3980a0223 (patch) | |
| tree | c8d18307aa41d357465d624eb474818aaf87b556 /drivers/gpu/drm/amd/display/dc/dc_dp_types.h | |
| parent | 589bd2f03f87563d6dc4f480d47e5aabc09e4784 (diff) | |
| download | linux-stable-edcf52caa985c010d0a6022190c8e3d3980a0223.tar.gz linux-stable-edcf52caa985c010d0a6022190c8e3d3980a0223.tar.bz2 linux-stable-edcf52caa985c010d0a6022190c8e3d3980a0223.zip | |
drm/amd/display: fix register write sequence for LINK_SQUARE_PATTERN
[why&how]
write LINK_SQUARE_PATTERN_num + 1 for square pulse pattern.
Specs requirement to write this register prior to write LINK_QUAL_LANEX_SET.
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_dp_types.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index bc87ea0adf94..e68e9a86a4d9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -898,6 +898,9 @@ struct dpcd_usb4_dp_tunneling_info { #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 #endif +#ifndef DP_LINK_SQUARE_PATTERN +#define DP_LINK_SQUARE_PATTERN 0x10F +#endif #ifndef DP_DSC_CONFIGURATION #define DP_DSC_CONFIGURATION 0x161 #endif |