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authorDillon Varone <dillon.varone@amd.com>2021-03-03 20:50:57 -0500
committerAlex Deucher <alexander.deucher@amd.com>2021-03-23 23:32:31 -0400
commit8c2f14c36f47ce60e7c021ce8901006524f6f40e (patch)
tree4faa1c09e9aad8844d2ae56a844bd11de17e90e0 /drivers/gpu/drm/amd/display/dc/dc_dsc.h
parent86ca3cbe5c9ca8e7d47424c98fc7b49b34b67d96 (diff)
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drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations
[Why?] Some code still expected bpp to be used in whole bits, not 16ths. dsc.c uses redundant function now found in dc to calculate stream bandwidth from timing. [How?] Fix code to work with 16ths instead of whole bits for dsc bpp. Refactor get_dsc_bandwidth to accept inputs in 16ths of a bit. Use dc function to calculate bandwidth from timing, and make dsc bw calculation a part of dsc.c. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_dsc.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_dsc.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index ec55b77727d5..0c5d98524536 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -51,6 +51,7 @@ struct dc_dsc_policy {
int min_slice_height; // Must not be less than 8
uint32_t max_target_bpp;
uint32_t min_target_bpp;
+ uint32_t preferred_bpp_x16;
bool enable_dsc_when_not_needed;
};
@@ -62,8 +63,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
bool dc_dsc_compute_bandwidth_range(
const struct display_stream_compressor *dsc,
uint32_t dsc_min_slice_height_override,
- uint32_t min_bpp,
- uint32_t max_bpp,
+ uint32_t min_bpp_x16,
+ uint32_t max_bpp_x16,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dc_crtc_timing *timing,
struct dc_dsc_bw_range *range);
@@ -77,8 +78,10 @@ bool dc_dsc_compute_config(
const struct dc_crtc_timing *timing,
struct dc_dsc_config *dsc_cfg);
+uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16);
+
void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
- uint32_t max_target_bpp_limit_override,
+ uint32_t max_target_bpp_limit_override_x16,
struct dc_dsc_policy *policy);
void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);